Satellite FPGA Engineer – Real-Time DSP, RTL & Equity

Yoh is seeking a Senior FPGA / RTL Design Engineer in Southampton. Hybrid role with 2 days onsite. You will design RTL IP for FPGA and ASIC, translating algorithms into efficient hardware and validating through timing closure and integration across the project lifecycle.

Ideal candidates have strong Verilog/SystemVerilog skills, experience in high-speed digital hardware or DSP, and a track record in complex FPGA/ASIC development. Wireless/AMBA experience is a plus.

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